1. Field of the Invention
The invention relates to devices for transferring signals between buses. More particularly, it relates to voltage translation and address multiplexing between different buses.
2. Description of the Related Art
Modern computer systems can permit a variety of memory components to be used in a single computer system. During initialization, the system queries the various memory components to determine their size and configuration, and writes the pertinent information into the appropriate locations for operational use of the memory. This communication is typically performed over a separate bus other than the normal memory bus used for memory read/write operations.
FIG. 1 shows a conventional system. During system initialization, system device 6 communicates over bidirectional serial bus 18 with multiple memory components, which are typically synchronous dynamic random access memories (SDRAM) 16. Each SDRAM includes a serial presence detect (SPD) circuit that receives queries from system device 6, and responds with information on the capacity and other parameters of the SDRAM. The information thus received by the system device is then used to configure the system to accommodate the various sizes and types of memory components that may be present. Once the system has been configured, normal read and write operations to memory take place through a different, higher speed data path (not shown).
Bus 18 is typically an inter-integrated circuit bus, frequently referred to as an I2C or I2C bus. This is a well-known two-line serial bus with a bi-directional serial data line and a bi-directional clock line. I2C protocol follows a master-slave format, with the master device initiating a transaction and specifying the address of the designated slave device, and the designated slave device responding to it. I2C protocol is fairly simple, with a five-part format: 1) A start bit to initiate a transaction, 2) an address byte, with seven bits denoting the address and the eighth bit denoting a read or write command, 3) data bytes, 4) an acknowledge bit following each 8-bit address or data byte, and 5) a stop bit to terminate the transaction. During the transmission of address and data bits, the data line may change only while the clock line is low. If the data line changes while the clock line is high, this signifies one of two commands: 1) a falling data signal from the master is a START command, and 2) a rising data signal from the master is a STOP command. An ACKNOWLEDGE response from the slave is indicated during an acknowledge bit when the slave pulls the data line low while the clock line is low, and keeps the data line low while the clock line is high. Failure of the slave to pull the data line low during the acknowledge bit is a non-acknowledgment condition and the master will abort the transfer with a stop bit. I2C protocol also allows a slow slave device to make the clock line wait for it. When a responding slave device sees the clock line pulled low, it can also drive the clock line low until it is ready to receive the next clock pulse. This period will normally be less than the period in which the master is driving the clock low (i.e., 4.7 microseconds minimum), and will therefore have no effect. But in the event the slave keeps the line low for longer than this period, the clock line will remain low even after the master device ceases driving it low. When this happens, the master device recognizes this condition as a delay by a slow slave, and delays the start of the next clock cycle until the slave releases the clock line, allowing it to go high.
Memory components such as SDRAMs 16 are typically designed to interface the I2C bus with 3.3 volt logic. However, many system devices now incorporate logic circuits using 1.8 volt logic levels, and can suffer damage if exposed to voltages in excess of about 2.2 volts. Thus, connecting these 1.8 volt system devices directly to a standard 3.3 volt SDRAM through an I2C bus can result in damage to the system device""s interface circuitry.
In addition to the above problems, limited addressability is also a problem. Although the I2C protocol provides seven address bits, four bits are usually pre-assigned for specific memory types and the remaining three bits can only address eight individual SDRAMs. Eight memory components is seldom enough.
An apparatus of the invention includes a first bidirectional data port operable at a first signal voltage level, and a second bidirectional data port operable at a second signal voltage level which may be different than the first signal voltage level. The apparatus also includes a first bidirectional clock port operable at the first signal voltage level and a second bidirectional clock port operable at the second signal voltage level. The apparatus further includes a system control circuit coupled to the first and second data ports and to the first and second clock ports. The first data and clock ports can communicate with a first serial bus and the second data and clock ports can communicate with a second serial bus.
A method of the invention for transferring bus signals between buses may include selectively and non-simultaneously performing each of the steps of a) repeating a clock signal from the first clock line to the second clock line and repeating a first data signal from the first data line to the second data line, b) repeating the clock signal from the first clock line to the second clock line and repeating a second data signal from the second data line to the first data line, and c) preventing the clock and data signals from the first clock and data lines from repeating on the second clock and data lines.